1. Field of the Invention
The present invention generally relates to a process of manufacturing semiconductor devices. More particularly, the present invention relates to a method of forming contact openings and a method of forming semiconductor devices.
2. Description of the Related Art
With rapid advancement in semiconductor fabrication technologies, the size of semiconductor devices has shrunk to deep sub-micron levels. As the level of integration of integrated circuits increases, the surface of a chip alone can hardly have sufficient area for accommodating all the interconnects. To provide necessary interconnects after device miniaturization, a design having two or more metallic interconnects is routinely used in very large scale integration (VLSI) packages. However, to connect two metallic lines at different layers, the intermediate insulating layer is bored to produce an opening and then a conductive material is deposited into the opening to form a conductive plug structure.
To combat the shrinking line width and prevent any misalignment of contact opening, most semiconductor devices employs a self-align contact design. This is particularly true in the design of a memory device. Typically, the doped region in a substrate and a bitline above the substrate are electrically connected through a self-aligned contact.
FIGS. 1A through 1F are schematic cross-sectional views showing the progression of steps for producing a conventional contact opening in a memory device. As shown in FIG. 1A, a substrate 100 having a gate structure 112 with a cap layer 110 thereon is provided. Each gate structure 112 comprises a gate dielectric layer 104, a polysilicon layer 106 and a metal silicide layer 108. The labeled region 102 is a prescribed region for forming a bitline contact while the labeled region 103 is a prescribed region where no bitline contact is formed.
As shown in FIG. 1B, a tungsten silicide etching process is performed to remove a portion of the sidewall of the tungsten silicide layer 108. Thus, the tungsten silicide layer 108a form a recess on the sidewall to neighboring film layers.
As shown in FIG. 1C, a thermal oxidation operation is performed to form an oxide liner 114 on the sidewalls of the gate structure 112 and the exposed substrate 100 surface. Because a portion of the metal silicide layer 108 on the sidewall has been removed, lateral extrusion caused by crystal growth on the metal silicide layer 108a can be avoided.
As shown in FIG. 1D, a photoresist layer 116 is formed over the substrate 100 covering the region 103. Thereafter, a sidewall oxidation layer etching operation is performed to reduce the thickness of the exposed oxide liner 114 and produce an oxide liner 114a. The purpose of reducing the thickness of the oxide liner 114 within the region 102 is to increase the width of the gap (opening) and reduce the aspect ratio so that the process window in subsequent etching or depositing operation can be increased.
As shown in FIG. 1E, the photoresist layer 116 is removed. A spacer 118 is formed on the sidewall of the gate structure 112 and the cap layer 110, for example, by forming a silicon nitride layer (not shown) over the substrate 100 and then perform an anisotropic etching operation. However, during the anisotropic etching operation, a portion of the exposed oxide liner 114a or the entire exposed oxide liner 114a may be removed due to a reduced thickness within the region 102. In other words, a portion of the substrate 100 will be exposed.
As shown in FIG. 1F, an insulation layer 120 is formed over the substrate 100. Thereafter, photolithographic and etching processes are carried out to pattern the insulation layer 120 and form a self-aligned contact (SAC) opening 122 within the region 102 between two neighboring gate structures 112.
Even though a portion of the substrate 100 within the region 102 has been exposed however, it is to be noted that portions of the substrate 100 may not be exposed in each and every contact openings in the other regions (not shown). The etching process of self-align contact opening directly etch through to substrate to ensure that portions of the substrate 100 are exposed within other contact openings. However, this practice may cause over-etching of the substrate 100 leading to some structural damage as shown by the numeral 117 in FIG. 1F.
In general, the region in the substrate 100 marked as 117 is a doped region (not shown). Hence, damaging the region 117 may lead to junction leakage problems. To compensate for the damage in the substrate 100, an additional ion implantation has to be carried out so that the correct dopant concentration is restored. Therefore, the processing step is not only more complicated but may also intensify short channel effect.